With a recent increase in the operation speed of an LSI, domino circuits are widely used as a means for increasing the operation speed of the LSI. Techniques related to the domino circuits include, e.g., “DOMINO CIRCUIT ARRANGEMENT” in Patent Document 1 and “SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS DESIGNING METHOD” in Patent Document 2.
The domino circuits are logic circuits that alternately perform two phases, which are (1) precharge using a clock (precharge phase) and (2) discharge by logic evaluation using an nMOS logic (evaluation phase), once during each clock cycle in synchronization with the clock.
Since the domino circuits do not use a pMOS in the logic evaluation as described in the above-mentioned (2), it is known that the domino circuits are higher in speed than typical static CMOS circuits.
On the other hand, as described in the above-mentioned (1), since the precharge operation is inevitably performed during each cycle in synchronization with the clock, power is consumed in each cycle. In other words, since the static CMOS circuits do not need clock signals for the operations thereof, the power is not consumed unless input signals operate. In contrast, the power consumption of the domino circuits is relatively large.
FIG. 1 shows a structure of the domino circuit. The domino circuit includes a pMOS transistor 101 for performing precharge, an nMOS 102 logic circuit for performing logic evaluation, and an inverter 103 to be added to an output. In the evaluation phase, the nMOS 102 logic circuit is appropriately turned ON when an input signal rises, performs discharge when logic is true, and holds the charge when the logic is false.
In this case, because the nMOS logic circuit 102 only includes a function of either discharging the charge or holding the charge, it is impossible to perform recharging in the evaluation phase if a charge once has been discharged, and it is necessary to wait for the next precharge phase in order to perform the recharging.
This means that the input signal of the nMOS is allowed only to make a transition in a rise direction in the evaluation phase, and not allowed to make a transition in a fall direction. This is because the transition in the fall direction means that the nMOS needs to be in an ON state (i.e., discharge state) from the start. Thus, it is impossible to perform the charging when the input signal falls as described above, and to perform the correct logic evaluation. A property in which the transition of the signal is performed only in the rise direction is called a monotonic property, and the monotonic property needs to be insured for the input signal of the domino circuit.
In a connection between the domino circuits, an effective method for insuring the monotonic property is a dual rail domino logic. A structure of the dual rail domino circuit is shown in FIG. 2. Signals indicated by “clk” in the drawing denote a clock signal which is distributed and inputted to all domino circuits. However, in order to avoid complication of the drawing, each of the signals is independently illustrated and is designated by the “clk”. In other words, the signals are independently illustrated in the drawing, but the same signal is actually distributed.
In the drawing, a dual rail domino circuit 112 includes typical domino circuits 110 and 111. The domino circuit 110 outputs High when the logic to be evaluated is true. In other words, the domino circuit 110 is based on positive logic. On the other hand, the domino circuit 111 outputs High when the logic to be evaluated is false. In other words, the domino circuit 111 is based on negative logic. To the domino circuits 111 and 112, arbitrary input signals In0 to InN (N is an arbitrary natural number) and their inverted signals are inputted.
Therefore, when the result of the evaluation is true, the output of the domino circuit 110 becomes High, while the output of the domino circuit 111 continues to be Low. On the other hand, when the result of the evaluation is false, conversely to the case shown above, the output of the domino circuit 111 becomes High, while the output of the domino circuit 110 continues to be Low. Due to this operation, the output signals unfailingly rise irrespective of whether the logic is the positive logic or the negative logic so that it becomes possible to safely compose the circuit using the domino circuit.
As described above, the dual rail domino circuit is an effective method for safely constructing the circuit when composing the domino circuit. However, since the circuit requires implementation of both of the positive logic and the negative logic, a power overhead is large. A method often used to suppress the power consumption includes a gating method.
The typical method is a method called clock gating. The clock gating is a method in which a logic circuit for selectively stopping the clock signal is incorporated in a clock generation/distribution circuit, and the supply of the clock signal to a block which is not required to use during the operation of the LSI is stopped so that the power consumption in the block is suppressed.
Because the clock as the basic signal for operating the logic circuit is stopped, it is possible to stop the operation irrespective of whether the target logic circuit is a typical CMOS logic circuit or the domino circuit.
In addition, when the clock can not be stopped for some reason (when the clock gating method can not be applied), it is possible to stop only data. This is a method in which a logical AND is generated using a gating control signal and the corresponding signal (data signal) and the transition of the corresponding signal is stopped when the gating control signal is disable. Because the present method does not have a commonly used name, the method will be described as a “data gating method” in the present description.
A structure of the domino circuit to which the data gating method is applied is shown in FIG. 3. There is adopted the structure in which target domino circuits 131, 132, 133, construct a stage 130, and a next stage 140 subsequent thereto is successively arranged. In order to apply the data gating method, a gating logic circuit 120 for implementing the logical AND of a gating control signal disable and the data signal is incorporated immediately previous to the stage 130, and it is possible to forcibly bring all signals into Low using the control signal disable. The signals fixed to be Low are propagated to the stage 130 to fix the output thereof to be Low. This operation is successively propagated to individual stages and all circuits are eventually stopped. The data gating can be achieved by this implementation.
The data gating method does not contribute to the power reduction in the clock distribution system when compared with the clock gating method. However, the data gating method allows control on a per signal basis so that it is possible to perform exacting control.
In addition, in the clock gating method, all logic circuits are simultaneously stopped. On the other hand, data is successively stopped in the data gating method. As a result, a noise in a power network is also reduced.    Patent Document 1: Japanese Unexamined Patent Publication No. 2004-173273    Patent Document 2: Japanese Unexamined Patent Publication No. 2006-253242